Re-factored fakeram to support sp/dp ram/regfile#7
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maliberty merged 1 commit intoJun 5, 2025
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Jun 4, 2025
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- Added support for single-port and dual-port RAMs and Reg Files
- The existing SP SRAM output was kept as-is for backward compatibility
- The other three memory types are all-new
- Added unit and flow tests to get coverage up to around 89%
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@maliberty, I can walk you through what I did, if you want. There are a lot of changes |
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fixed coverage instrumentation more cleanup and code coverage comment updates and parse_input.py removal Signed-off-by: Jeff Ng <jeffng@precisioninno.com>
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maliberty
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| def get_port_config(json_data): | ||
| if "port_configuration" in json_data: | ||
| return json_data["port_configuration"] | ||
| return "SP" |
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I think this can just be
def get_port_config(json_data):
return json_data.get("port_configuration", "SP")
same elsewhere
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